T. Bull, “Forward error correction and functional programming,” Master’s thesis, The University of Kansas, 2011.

Links

• http://www.ittc.ku.edu/csdl/fpg/files/Bull-11-FECandFP.pdf

Abstract

This thesis contains a collection of work I have performed while working on Dr. Erik Perrins’ Efficient Hardware Implementation of Iterative FEC Decoders project. The following topics and my contributions to those topics are included in this thesis. The first topic is a Viterbi decoder implemented in the Haskell programming language. Next, I will briefly introduce Kansas Lava, a Haskell DSL developed by my advisor, Dr. Andy Gill, and other students and staff. The goal of Kansas Lava is to generate efficient synthesizable VHDL for complex circuits. I will discuss one such circuit, a large-scale LDPC decoder implemented in Kansas Lava that has been synthesized and tested on FPGA hardware. After discussing the synthesis and simulation results of the decoder circuit, I will discuss a memory interface that was developed for use in our HFEC system. Finally, I tie these individual projects together in a discussion on the benefits of functional programming in hardware design.

BibTeX

@mastersthesis{Bull:11:FECandFP,
  author = {Tristan Bull},
  title = {Forward Error Correction and Functional Programming},
  school = {The University of Kansas},
  year = {2011},
}